1. Field of the Invention
The present invention relates to a memory device and a semiconductor device including the memory device.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory), which is one of semiconductor memory devices (hereinafter, also referred to just as memory devices), has a simple structure in which a memory cell includes a transistor and a capacitor (hereinafter, also referred to as a capacitor element). Thus, a DRAM needs fewer semiconductor elements for forming a memory cell than other memory devices such as an SRAM (Static Random Access Memory); therefore, memory capacity per unit area can be increased and cost can be reduced as compared to other memory devices.
A DRAM is advantageous for large storage capacity as compared to other memory devices; however, memory capacity per unit area needs to be further increased as in other memory devices in order that an LSI having higher degree of integration is realized while an increase in a chip size is suppressed. For that purpose, the area of a memory cell needs to be reduced; however, as the capacitance value is decreased due to reduction in the area of a capacitor element, difference of the amount of electric charge between the digital values becomes smaller. Accordingly, frequency of refresh operations needs to be increased and power consumption is increased. Thus, when memory capacity per unit area in a DRAM is increased, the area of a memory cell needs to be decreased while the capacitance value of a capacitor is ensured above a certain amount.
Patent Document 1 below discloses a structure of DRAM in which a bit line and a word line are shared with each other and the area of a memory cell is decreased with the use of transistors of different conductive types for a first memory cell and a second memory cell.
[Reference]
    [Patent Document 1] Japanese Published Patent Application No. 7-312392